The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a flash memory and a method for fabricating the same, which is suitable for improving the efficiency of programming and erasing operations.
Generally, a flash memory is a nonvolatile memory that is capable of being electrically reprogrammed. The principle of programming data in a memory cell will be explained below.
For programming, hot electron injection is used similar to the process used in programming a general electrically programmable read only memory (EPROM). That is, a high voltage is applied to a control gate for the purpose of injecting electrons generated from around the drain of a memory cell into a floating gate. Accordingly, if electrons exceeding a predetermined amount are injected into the floating gate, the threshold voltage V.sub.th of the memory cell transistor is increased. Information in the form of a "0" or "1" is determined by the threshold voltage difference between the increased threshold voltage and the threshold voltage of the memory cell transistor into which electrons are not injected.
For reprogramming information, the threshold voltage of the memory cell transistor returns to its initial value according to the migration of electrons injected into the floating gate by means of Fowler Nordheim tunneling. This uses the flash memory's inherent erase gate.
A conventional method for fabricating a flash memory will be explained below with reference to the accompanying drawings.
FIG. 1 represents the layout of a conventional flash memory. Field oxide layers 2 are selectively formed on a substrate 1, and a first n-type polysilicon layer is patterned to form a floating gate 3. A second n-type polysilicon layer is patterned to form a control gate 4, which is aligned in a perpendicular relationship to floating gate 3.
FIGS. 2A to 2D are cross-sectional views showing a method for fabricating the conventional flash memory. Referring to FIG. 2A, a tunneling oxide layer 5 is formed on a p-type semiconductor substrate 1, and a first n-type polysilicon layer 3 for the floating gate is formed on tunneling oxide layer 5. Referring to FIG. 2B, an insulating layer 7 and second n-type polysilicon layer 4 for the control gate are sequentially formed on first n-type polysilicon layer 3.
Referring to FIG. 2C, a photoresist pattern (not shown) is formed on the second n-type polysilicon layer 4. Selective portion of the second n-type polysilicon layer 4, insulating layer 7, first n-type polysilicon layer 3 and tunneling oxide layer 5 are then removed through photolithography.
Referring to FIG. 2D, impurities are ion-implanted into substrate 1 using the second n-type polysilicon layer 4 as a mask, to form source and drain impurity regions 8 and 9. Here, source impurity region 8 is formed into a deep junction for the purpose of the erase operation of the memory cell.
The programming of the flash memory is accomplished by injecting hot electrons generated from the channel 5 into the floating gate 3. Here, the ratio of the voltage applied to the floating gate to the voltage applied to the control gate for the purpose of forming the channel is called the coupling ratio. The programming efficiency of the device is increased as the coupling ratio becomes larger. The erasure of electrons injected into the floating gate is accomplished by Fowler-Nordheim tunneling while a positive voltage is applied to the deep junction of source region 8. Here, in order to increase the erase efficiency, tunneling oxide layer 5 under the floating gate is formed to be thin, and the floating gate and control gate are formed of n-type polysilicon.
FIGS. 3A and 3B show energy band diagrams taken along line B--B' of FIG. 2D. FIG. 3A is an energy band diagram of the device in an equilibrium state. Here, when a positive voltage is applied to the source region 8 for the erase operation, the energy band diagram is changed as shown in FIG. 3B. That is, the energy band of the tunneling oxide layer 5 becomes steeply sloped according to the positive voltage applied to source region 8. By doing so, electron tunneling occurs through a thin portion of the energy barrier of the tunneling oxide layer 5 when performing the erase operation.
However, the aforementioned conventional method for fabricating the flash memory has the following problems. First, while the oxide layer under the floating gate is used as the tunneling oxide layer in order to increase the erase process efficiency, the programming efficiency is decreased. Secondly, the tunneling oxide layer is severely damaged from the hot electron injection, deteriorating the reliability of the memory cell. Thirdly, a high voltage must be applied to the source for the erase operation since the floating gate is formed of n-type polysilicon.